Manufacturing and production industries use automatic test equipment (ATE) to analyze and assess integrity and operability of manufactured products at various stages of production. Robotic manipulator machines are often employed during testing by ATE to manipulate work pieces and products into and out of connection with the ATE. The semiconductor devices under test (DUTs) are presented to a test site of the ATE by the robotic machine, tested by the ATE, and then sorted and dispensed by the robotic machine into groups or bins (or otherwise according to an applicable scheme) according to test results. Because many diverse types of DUTs are tested by ATEs, and DUTs may be tested at various stages of production (e.g., final test, work piece probe, etc.), ATEs are varied in design according to the particular purpose, device, and/or product for testing. Similarly, robotic manipulator machines vary according to application and compatibility with the ATE.
Although varied, ATEs and robotic manipulators each usually include several typical operational units. ATEs and robotic manipulators are widely used, for example, in the production of electronic products, such as analog and digital components, circuits and devices (including semiconductors, integrated circuits, microprocessors, and the like). Because of this prevalence, the typical operational units of ATEs and robotic manipulators for such products are described.
The ATE includes a system controller, which controls the system and movement of data into and out of the system. The ATE also includes test data and test program storage, pattern memory, system power supplies, direct current reference supply unit, analog current reference supply unit, system clocks and calibration circuits, timing and time set memory, and precision measurement units (which may include digital, analog or mixed signal test resource circuitry). In addition, a test head of the ATE includes pin electronics driver cards providing pin circuitry (such as for comparators, current loads and other test resources) for pin electronics testing of DUTs. A device interface board (DIB) (also referred to as “load board) connects to the test head and provides connection socket(s) for the DUT or DUTs, as applicable. The ATE also includes external interfaces for connection to robotic manipulators for test devices (referred to as “handlers” or “device handlers”), as well as interfaces to computers, networks, and/or other instruments, devices or components.
Robotic manipulators, i.e., handlers, include mechanical systems and controllers. The mechanical systems physically deliver DUTs for presentation to the socket(s) of the DIB connected to the test head of the ATE, deposit the DUTs in the socket(s) during testing, remove the DUTs from the socket(s) post testing, and sort the DUTs according to respective test result after testing. The controller directs operations of the mechanical systems of the handler and communicates with the ATE. As required, handlers can include additional features of memory and specific units according to application and testing environment.
In conventional testing of devices by an ATE and mechanical manipulation of devices by a handler, the ATE commences testing each device when deposited by the handler in a socket of the DIB connected to the test head. When testing is completed, the handler must remove the tested device from the socket and transport a next device to the socket for testing. The time delay between testing by the ATE, during which devices are removed and transported from sockets and next devices are transported to and deposited in sockets, is referred to as “index time” for the test operation. Further, in conventional testing of devices by an ATE, the time required to test each device once deposited in a socket is referred to as “tester time” for the test operation. When testing a batch of devices, the total time required for the testing operation is the aggregate of the index time plus the tester time for all of the devices. Each device (or set of devices, if more than one device can be concurrently tested by the ATE in available sockets of the DIB) requires the sum of the index time plus the tester time for testing of the device. Although testing operations can also require additional time, for example, because of downtime of equipment, faults, or other impediments to continuous testing sequence, these are irregular and uncertain events that are not necessarily controllable.
Therefore, reducing the total test time (index time plus tester time) is desirable. Testing operations can require significant amounts of time, effort, and expense, such as for personnel, ATE, and handler equipment. ATEs are typically expensive because they are comprised of complex electronics. Handlers are generally less expensive than ATEs because mechanical pieces are controlled by less complex electronics. In efforts to receive greater returns on investments in ATEs and handlers, companies operating the equipment desire that idle times (periods of no testing) for this equipment be limited. Therefore, with ATEs and handlers, a reduction of total test time (index time plus tester time) can provide significant advantage. For example, if total test time is reduced, more testing can be performed by each piece of equipment and testing personnel during any period, leading to a greater investment return.
A primary focus in handler development has been to increase the speed of mechanical structures, such as arms, chucks, guides, cams and the like, in order to obtain shorter index times. Because handlers are generally less expensive than ATEs, older handler models are replaced with newer, speedier models. Older handlers become idle and obsolete. Handler mechanical failure is a significant source of testing downtime; therefore, excess handlers are often maintained as backup equipment, but stand idle during periods not in use with ATE for testing operations. It would be desirable to reduce total test time by the more effective and efficient use of ATEs and available handlers.
It would, therefore, be advantageous to reduce total test time for testing by reducing index time of handler/robotic manipulator operations. It would also be advantageous to efficiently use ATE resources and available handlers to put to use idle equipment, maximize use of equipment capabilities, take advantage of available capacity (including capacity from existing older equipment), and consequently, provide a better return on investment. Therefore, a platform system for reducing total test time, by decreasing handler index time and efficiently using automatic test equipment resources, would be a significant improvement in the art and technology.
Frequently, semiconductors need to be tested at different temperatures to insure operational effectiveness and efficiency of the semiconductor. Testing semiconductors at multiple temperatures during a single semiconductor test insertion provides several benefits. Single semiconductor testing is characterized by inserting the semiconductor into a testing socket at the handler testing site and performing multiple tests at different temperatures before removing the semiconductor from the testing socket at the handler testing site. However, conventional testing protocols for testing have been characterized by significant amounts of index time. A representative example of a conventional testing protocol for testing semiconductors at different temperatures is illustrated in Prior Art FIG. 1.
Prior Art FIG. 1 illustrates a simple single test insertion protocol, whereby testing is performed at three different temperatures. More specifically, in the illustrated example, the testing sequence is to first perform a cold temperature test, to secondly perform a room temperature test, and to lastly perform a hot temperature test. The actual temperatures for these tests would be dependent upon the particular testing protocol being utilized. Ramp time, which is illustrated as “ramp,” refers to an indexing time period in which the handler ramps to one of selected multiple testing temperature different from the preceding temperature. In other words, ramping refers to increasing or decreasing the temperature level from one testing temperature level to a different testing temperature level, while the semiconductor device remains inserted into a testing socket, but is not being tested. In this instance, time spent by the handler ramping from one testing temperature to another testing temperature is characterized as index time, i.e., time when the tester is idle and is not performing testing.
Again referring to Prior Art FIG. 1, the illustrated sequence begins with a ramp period wherein the handler ramps from an initial temperature, which is frequently the testing room (i.e., ambient) temperature, to a cold temperature so that a cold test can be performed. Upon completion of the cold test, the sequence ramps the temperature to room temperature so that a room temperature test can be performed. Upon completion of the room test, the sequence ramps to a hot temperature so that a hot test can be performed. Upon completion of the hot test, the sequential testing is complete for a first insertion cycle. In order to begin the second insertion cycle, the sequence ramps from the completed hot test in the first insertion cycle to the cold temperature so that the cold test for the second insertion cycle can be performed. The number “n” of insertion cycles for a particular test is determined by the size of the lot of the semiconductor devices to be tested divided by the degree of testing parallelism, which refers to the number of semiconductor devices that can be tested simultaneously by the tester and handler.
As described above in reference to Prior Art FIG. 1, for each semiconductor insertion cycle, which corresponds to one three-temperature testing sequence, there are three ramping periods that are characterized as index time wherein the tester is idle. Thus, the total time spent ramping while testing the entire lot of semiconductor devices is the accumulation of the time accrued during the three ramping period in each insertion cycle multiplied by the number of required insertion cycles. Dependent upon the capabilities of the handler, this total ramp time can be a significant source of inefficiency of the tester and handler that counteracts the benefits of conducting a single insertion test.